transistor Q17 conducts to supply a near ground
core near plug P1. The antenna passes through this
potential to diode CR16 to drive the servo motor to-ward
core and, with the permeability of the core being
minimum capacity. With a logic "O" on the base of Q17,
changed, the core acts as a small variable series
transistor Q17 biases off and permits the antenna
coupler to seek a null.
antenna between the variable capacitor C1 capacitance
values provided by the motor steps.
Manual Override Logic Analysis
The manual override logic provides a means of tuning
Transmit/Receive Circuit Analysis
the antenna without applying transmitted power.
a. Under normal conditions, a logic "1" input is
The transmit/receive circuit detects when RF power is
supplied to A6B-5, A6B, A6C-8, A6C-9, and the base of
supplied to the antenna and uses this signal to enable
transistor Q16. With a logic "1" on both inputs of NAND
the tuning circuits.
gate A6B, a logic "O" is supplied to NAND gate A6A.
the antenna RF input is keyed, the RF-on circuit detects
CR18 and CR23, permitting the normal homing logic and
the keyed RF power through CR3, providing a negative
transmit/receive signals to be passed. A logic "1" on the
voltage at the base of Q13. Transistor Q13 biases off
inputs of NAND gate A6C, used as an inverter, supplies
supplying a logic "1" to A4A-2 and A4B-7. This enables
a logic "O" to the base of transistor Q15. Transistor Q15
the tuning logic of the antenna coupler.
is biased off, supplying a logic "O" to the base of
transistor Q15. Transistor Q15 is biased off, supplying a
the RF input is not keyed, CR3 biases off. With CR3
logic "1" to diode CR19, disabling the manual override
biased off a positive potential is supplied to the base of
logic in-crease frequency signal. A logic "1" on the base
Q13. Transistor Q13 conducts to sup-ply a logic "O" to
of transistor Q16, causes Q16 to conduct and sup-ply a
A4A-2 and A4B-7, providing a lock-on voltage for the
logic "O" to diode CR20, disabling the manual override
logic decrease frequency signal.
b. With a ground supplied to decrease
Homing Logic Analysis
frequency, a logic "O" is supplied to the base of Q16 and
A6B-5. NAND gate A6B supplies a logic "1" to A6A.
The homing logic supplies a homing signal to re-turn the
NAND gate A6A supplies a logic "O" through CR18 and
antenna tuning capacitor to minimum after it has reached
CR23 to the base of Q17 and base of Q13. Transistor
Q17 biases off, supplying the normal tuning signal to
a. The homing logic is controlled by the limits
CR16. Transistor Q13 biases off, supplying A4A-2 and
of variable capacitor C1. When capacitor C1 reaches
A4B-7 with a logic "1" RF-on signal, enabling the tuning
maximum capacitance, limit switch S2 closes to supply a
logic. With a logic "O" input at transistor Q16, Q16
logic "O" to A5C-8. NAND gate A5C supplies a logic "1"
biases off and supplies a logic "1" to CR20, causing the
from A5C-11 to the base of transistor Q17 and A5D-12.
coupler to tune toward maximum capacitance of the
NAND gate A5D has a logic "1" input on pin 13 while limit
antenna tuning capacitor thereby reducing the resonant
switch S1 is open. NAND gate A5D with both logic "1"
inputs supplies a logic "O" to A5C-9. This logic "O" is
c. With a ground supplied to increase
also supplied through CR29 to the base of Q13 (units
frequency, diode CR26 conducts supplying a logic "O" to
MCN 1740 and above). Transistor Q13 is biased off and
A6C-8, 9 and A6B-6 NAND gate A6B sup-plies a logic
a logic "1" is supplied from the collector of Q13 to enable
"1" to A6A. NAND gate A6A sup-plies a logic "O"
the tuning logic circuits. Upon initial application of power,
through CR18 and CR23 to the base of Q17 and the
the antenna tuning capacitor is driven to minimum
base of Q13. Transistor Q17 biases off, supplying the
capacity (units MCN 1740 and above). The above
normal tuning signal to CR16. Transistor Q13 biases off,
conditions remain until C1 reaches its minimum
supplying A4A-2 and A4B-7 with a logic "1" RF-on signal,
capacitance where Si closes and sup-plies a logic "O" to
enabling the tuning logic. NAND gate A6C with logic "O"
A5D-13. NAND gate R5D supplies a logic "1" to A5C-9;
inputs supplies a logic "1" output to the
a logic "1" is also supplied to A5C-8 because limit switch
S2 is open. Therefore, NAND gate A5C with both logic
"1" inputs supplies a logic "O" input to the base of Q17
b. With a logic "1" on the base of Q17,